Industrial Automatic Control Systems and Controllers Annotation << Back Synthesis and Programming of Hardware Accelerator Based on PLD in Xilinx CAD Ya.A. Divakova PLDs are part of a hardware method for accelerating the work of the developed encryption algorithms. The most popular are PLDs with FPGA architecture. These chips are in demand due to their speed and the ability to reprogram the encryption algorithm. The article includes all the stages of designing an arithmetic logic unit: implementation based on the minimum DNF, implementation on logical generators, an encryption algorithm in the Verilog description language is developed, the general structure of the PLD is implemented, and the design of the arithmetic logic unit is tested, implemented in the scope of the Spartan-3E PLD. The problem of unlimited reprogramming of the device using the Verilog description language has been solved. The possibilities of development of software and hardware systems in Xilinx CAD are investigated. Keywords: arithmetic logic unit; programmable logic device; computer-aided design; chip; description language. DOI: 10.25791/asu.12.2020.1242 Pp. 27-31.